A digital phase lock loop (DPLL) uses a phase detector to detect a phase difference between a reference signal and a digital controlled oscillator signal. If the edges of digital oscillator (DO) signal are counted the phase of the DO is quantized with accuracy of one DO period. The reference counter accumulates, at every reference clock cycle, a tuning word that express the channel in the units of the reference frequency. In this way the reference counter defines the time points where the DO should be. The phase detector measures the difference between two counters and produced correction signal for the loop.
U.S. Pat. No. 6,429,693 discloses a fractional phase detector that provides for a more refined measurement of phase difference, with an accuracy corresponding to a fraction of the clock period. This may be realized by using a chain of delay circuits to generate successively more delayed versions of the clock signal and sampling these versions at the time of a transition of the reference signal. The delays differ by fractions of the signal periods. From the sampling result the time delay between the clock signal and the reference signal can be determined, expressed in terms of the time delays of the delay circuits. This type of operation is called time to digital conversion (TDC).
Unfortunately, a TDC measures time rather than phase. U.S. Pat. No. 6,429,693 mentions that to convert the measured time into phase, the delay has to be divided by the length of the period of the clock signal, also expressed in terms of the delays of the delay circuits. U.S. Pat. No. 6,429,693 avoids performing this conversion, because it only uses the time measurement as an error signal. However, U.S. Pat. No. 6,429,693 illustrates a phase computation wherein time delays are determined between the transition of the reference signal and both a positive and a negative transition of the clock signal, each in terms of time delays of the delay circuit. The difference between the two time delays represents the time interval between the positive and negative transitions of the clock signal. This difference is used to normalize a time measurement between a transition of the clock signal and the transition of the reference signal. Thus, a phase value is obtained. However, this method may not produce useful result when the period of the reference signal is an integer multiple of the clock signal. Also, different reaction times of the delay line to logical up-down and down-up transitions may affect accuracy.